Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a circuit for generating an output pattern of an error code and a semiconductor memory device including the same.
As semiconductor design technologies are being advanced and operational speeds of systems are becoming faster, circuit devices for receiving data, storing the received data, and outputting stored data are to operate at a high speed. Accordingly, a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device has been implemented with a Double Data Rate (DDR) method for inputting/outputting data in synchronization with a falling edge of a system clock as well as the rising edge of the system clock. Recently, a DRAM device using DDR2 and DDR3 method for inputting/outputting 4-bit or 8-bit data per one clock cycle has been used.
However, as a data transfer speed of the circuit devices becomes faster, a probability of a data transfer error also increases. Thus, a device and method to secure the data transfer is useful. In obtaining such a feature, an error code for verifying an error is generated whenever data are generated, and the error code is transferred along with the data. Such an error code includes an Error Detection Code (EDC), which is used in detecting the generated error, and an Error Correction Code (ECC), which is used to correct the error if an error occurs.
FIG. 1 is a block diagram of an error code generation circuit used in a conventional semiconductor memory device.
Referring to FIG. 1, the error code generation circuit includes an error code generation unit 101, a storage unit 103 and an output unit 105.
The error code generation unit 101 is configured to generate an error code ECODE<0:7> by using read data RDATA<0:63> in response to a read command RD or using write data WDATA<0:63> in response to a write command WT. Here, the read data RDATA<0:63> are composed of 64-bit parallel data, which are outputted to outside from a memory cell region of the semiconductor memory device (not shown), and the write data WDATA<0:63> are composed of 64-bit parallel data, which are inputted to the semiconductor memory device from the outside. The error code ECODE<0:7> is composed of 8-bit parallel data. For example, the error code generation unit 101 may generate the 8-bit error code ECODE<0:7> as an error detection code (EDC) by performing Cyclic Redundancy Check (CRC) using a CRC-8 calculator on the 64-bit read data RDATA<0:63> or the 64-bit write data WDATA<0:63>.
The storage unit 103 is configured to temporarily store the error code ECODE<0:7> and output the stored code as an error data P_ECODE<0:7> in synchronization with a system clock. As shown in FIG. 2, the storage unit 103 may comprise first to eighth pipe registers PIPE_0 to PIPE_7 for storing the error code ECODE<0:7> bit-by-bit. Each of the first to eighth pipe registers PIPE_0 to PIPE_7 stores a corresponding one of bits ECODE<0> to ECODE<7> in response to an input control signal PIN and outputs the stored bit to the output unit 105 in response to an output control signal POUT.
The output unit 105 is configured to output the error data P_ECODE<0:7> to the outside of the semiconductor memory device through an output pad 107. The output unit 105 is implemented with a parallel-to-serial converter for receiving the error data P_ECODE<0:7>, which is transferred in parallel from the storage unit 103, and converting the error data P_ECODE<0:7> to data in series.
FIG. 3 is a timing diagram illustrating an operation for generating and outputting the error code ECODE<0:7> in the semiconductor memory device of FIG. 1.
Referring to FIG. 3, when the read command RD is inputted to the semiconductor memory device, the read data RDATA<0:63> is transferred to the error code generation unit 101 in parallel from a memory cell region through global data lines (GIO). The error code generation unit 101 generates the 8-bit error code ECODE<0:7> based on the read data RDATA<0:63>. The storage unit 103 temporarily stores the error code ECODE<0:7> in response to the input control signal PIN and outputs the error data P_ECODE<0:7> to the output unit 105 in response to the output control signal POUT. The output unit 105 converts the error data P_ECODE<0:7> in series, and outputs the serialized error data P_ECODE<0:7> to the outside of the semiconductor memory device through the output pad 107.
Here, an error code generation circuit used in a semiconductor memory device or a communication device is to be operated at a high-speed. However, in case where an external device for testing these devices cannot keep up with an operational speed of the error code generation circuit, the external device fails to recognize an error code outputted from the error code generation circuit. For example, when the semiconductor memory device outputs an 8-bit error code at a speed of 1 GHz and the external device for testing the semiconductor memory device operates at a speed of 500 MHz, the external device may recognize only 4-bit error code among the 8-bit error code which is outputted in series from the semiconductor memory device.